چکیده:
A low noise amplifier is designed and simulated for the frequency range of 3.1 to 10.6 GHz using CMOS 0.18 μm technology. In this design there is a common source stage with an inductor in the source in order to reduce the amount of noise. The second stage is a structure to reuse the current in order to increase the gain and decrease the power consumption. Moreover, an NMOS transistor is used to improve the linearity of the proposed circuit. The proposed design is then simulated using the 0.18 μm CMOS technology in ADS software. The results show a noise level of less than 3dB and a flat gain of 14dB, also the IIP3 factor of the circuit is measured to be 0.5dBm which indicates the high degree of linearity in the circuit. The circuit power consumption is 23 mw.
خلاصه ماشینی:
In order to achieve low noise and power in this design, a two stage CMOS DA along with current-reuse technique and noise elimination is used.
Noise Figure (NF) simulation for 3-11 GHz frequency range a) before linearity improvement b) after linearity improvement By performing a DC circuit analysis and calculating the product of the supply voltage and bias voltage in the current drawn from them, the power consumption of the two circuit are obtained and compared as follows.
Power consumption calculation of the low noise amplifier before linearity improvement Fig. 9.
Power consumption calculation of the low noise amplifier using linearity improvement technique Another important factor in the LNA specification is the 1dB compression point.
Given the curve shown in Fig. 11, the simulated for the low noise amplifier after applying the linearity improvement technique is 9.
Low noise amplifier IIP3 calculation a) original design b)using linearity improvement technique By definition, IIP3 is the amount of input power in which the main output and harmonic power curves collide.
With respect to the above curve, the IIP3 value of the low noise amplifier by applying a linearity improvement technique is approximated by 0.
In final step low noise amplifier circuit stability diagram with linearity improvement technique is illustrated in Fig. 13.
Low noise amplifier circuit stability diagram with linearity improving technique The results obtained from the simulation of the original circuit and the improved design are summarized in Table.
Sánchez-Sinencio, "Linearization techniques for CMOS low noise amplifiers: A tutorial," IEEE Transactions on Circuits and Systems I: Regular Papers, vol.