چکیده:
The increased use of Portable electronics devices such as cellular phones, notebook and computers has made power dissipation an important design metric in modern microelectronics. Portable devices that operate using a battery have limited energy supplies and thus have lifetime that are constrained by their power consumption. Even ICs in systems that are plugged into a continuous power supply are becoming power constrained due to the difficulty of dissipating heat that results from consuming power on a chip with many tightly packed transistor. Our objective is to reduce power dissipation in digital CMOS VLSI circuits.later; we will compare all the optimal methods which can reduce maximum power dissipation among all and with fewer limitations. We have used Galaxy Custom Designer a tool of Synopsys and SPICE coding to find out delay, power, energy and leakage charge with the various design styles like CMOS, Pass transistor, DCVS (Differential cascade voltage switch logic circuit), Dynamic, DCVS-PG. We had computed the delay, power, energy and power leakage and compared amongst these design styles to conclude which design style would work for the specific requirement.
خلاصه ماشینی:
"We have used Galaxy Custom Designer a tool of Synopsys and SPICE coding to find out delay, power, energy and leakage charge with the various design styles like CMOS, Pass transistor, DCVS (Differential cascade voltage switch logic circuit), Dynamic, DCVS-PG.
123 350 300250 200 150 100 50 0 100 Mhz 200 Mhz 300 Mhz 500 Mhz CMOS Pass Gate DCVS Dynamic DCVS-PG Graph1: Average power presentation with frequency variations in different design styles.
Table 2: fix input parameter during work It has been observed that The Ratioed and Pseudo have power dissipation more than other design styles, while CMOS and Dynamic implementations shows low Power Dissipation.
3. 2 DELAY - we can find the delay by the following formula, ⁄ =TIME taken by output to change from high to low state =TIME taken by output to change from low to High state With the same input values we find the delay with various techniques and results are as follows –University College of Takestan Table 4: Delay of design styles with frequency (in ns) 20 15 10 5 CMOS Pass DCVS Dynamic DCVS PG 0.
Comparison between 2 best Design Styles - We have seen that if we take Power Consumption and Delay and energy and Leakage power as our parameters and we compare all the design styles as we did earlier than we could come up with the 2 best design styles, they are – CMOS and Dynamic So we will now cross-check for Half – adder circuit and will determine whose design style is better at what conditions."